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Research / Sega's SVP Chip / Official chip description According to the manual: Samsung is a pioneer in the DSP core approach, which is a high performing and flexible family of DSP core based ASDSP (Application Specifics Digital Signal Processor). The DSP core architecture and instruction set are designed simplicity and flexibility. The DSP core contains only the most essential DSP function blocks. Because all internal buses are accessible externally. The ASDSP is an application specifics integrated sircuit that incorporates a programmable digital signal processor core. The ASDSP approach allows the system designer to integrate a programmable dsp core, interface logic, peripheral, extra memory into a single integrated circuit. Typically, the custom circuitry on a ASDSP is implemented either in standard cell or gate array. All methods used samsung process by 0.8um double metal CMOS technology. The SSP1601 uses 0.8um CMOS technology (CSP4H) and can perform up to 25 MHz at 5V. The SSP1601 DSP cores have the following on-chip functions: The DSP core can address up to 64K-word of external ROM over an external data bus. The actual size of the external ROM area used depends upon the requirements of the individual application. The SSP1601 has five 16-bit buses and one 32-bit bus: MPYA instructions (add, load, multiply, and modify RAM address pointer) are executed efficiently within one machine cycle. The condition flags in the status register (ST) are set or cleared by the corresponding ALU operations. Values for the status register control bits are loaded by application software or through the I/O pins USR0, USR1, ST5 and ST6. The system stack has six hardware levels and operates using Push and Pop operations. The pins EA[2:0], ESB and R/WB are used to control the EXT bus, and the RESB, INT0, INT1, INT2 and SS pins are used to control system functions. Back | Printer friendly 2. List of features >> |