Research / Sega's SVP Chip / Pin layout - explained
Name | Number | I/O | Description |
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CK1 | 51 | I | Clock | PH10B | 52 | O | Internal clock output Inverted output of PH1 generated from CK1 | RESB | 50 | I | Asynchronous step Effective when SK1 is rising | SS | 53 | I | Asynchronous single step Effective when CK1 of a cycle is rising | INT0 INT1 INT2 | 56 57 58 | I | Interrupt request 0 Interrupt request 1 Interrupt request 2 | PA0-PA15 | 27-35 & 37-43 | O | Program address | PD0-PD15 | 11-26 | I/O | Program data | EXT0-EXT15 | 1-9 & 61-68 | I/O | External data bus | EA0-EA2 | 44-46 | O | External register address | ESB | 47 | O | External data strobe | R/WB | 48 | O | Read/write timing signal for EXT bus | USR0 USR1 | 54 55 | I | User input 0 User input 1 | VDD | 36, 49 | I | +5 Volt | VSS | | I | GND | ST5 ST6 | 59 60 | O | User output 0 User output 1 |
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